In multi-level metal interconnection layers, it is required for adequate planarity and yield that there be vertical conductive members, referred to as studs, connecting one level of interconnection with another. This requirement results from the fact that thin metal going over corners or into an aperture between layers tends to cover poorly and thus to detract from adequate yield. Further, tapered vias use more area than vertical vias, thereby reducing usable device density.
When an upper metal layer (e.g. Al) over a preexisting stud is patterned in a reactive ion etch (RIE) process and the wire is borderless to the stud and made of the same material or a material etched by the same gases, the inevitable misalignment exposes part of the stud to the etching gases, so that a portion of the stud is removed, as shown in FIG. 2. If tungsten (W) is used as a stud material below Al, little stud material is removed, but the finished structure contains a W-Al interface that degrades electromigration resistance through flux divergence and blockage of the transport of Cu alloying atoms. In addition, W has low conductivity. If an Al stud is used instead of W, conductivity and reliability are improved, but damage to the stud by wire RIE is increased, reducing yield and reliability.
In a less conventional method, monolithic stud/wires can be constructed by filling a via hole with metal in such a manner as to leave a largely planar overburden. Wires are then formed by patterning the overburden. This process has lower cost and enhanced intrinsic material reliability compared to the discrete stud/wire approach, but suffers from the same problem of stud damage during wire level RIE. In high density layouts, where the tolerances are reduced to the extent that a wire over the stud has the same dimension as the stud, so that there is only partial overlap of the wire, inevitable misalignment will also expose the stud to the etching gases.